1. Field of the Invention
This invention relates generally to frequency synthesizers, and relates more particularly to a novel frequency divider circuit for use in programmable frequency synthesizers.
2. Description of the Relevant Art
A programmable frequency synthesizer is a device that is capable of generating a signal having a frequency selected from within a range of frequencies. A typical programmable frequency synthesizer utilizes a digital phase-locked loop circuit that uses a voltage controlled oscillator (VCO) to generate the synthesizer output signal. The phase-locked loop includes a feedback and control loop that monitors the frequency of the synthesizer output signal, compares its frequency to that of a reference signal, and directs the VCO to adjust the frequency of the synthesizer output signal accordingly. In the feedback portion of the loop, the synthesizer output signal is divided by a digital frequency divider, which generates a feedback signal having a frequency that is a selected sub-multiple of the synthesizer output signal. The phase or frequency of the feedback signal is compared to that of a stable reference signal and the difference between the two signals defines an error signal that is filtered, amplified, and fed back to the VCO. The VCO adjusts the frequency of the synthesizer output signal in order to reduce the error signal. The reference signal has a lower frequency than the synthesizer output signal since lower frequency oscillators exhibit better long-term stability.
Frequency selection of the synthesizer output signal is provided by the programmability of the frequency divider, which divides the synthesizer output signal by a selectable divider number that is chosen to be equal to the desired frequency of the synthesizer output signal divided by the frequency of the reference signal. To change the frequency of the synthesizer output signal, one selects a different divider number. The range and step size of the discrete frequencies that a programmable frequency synthesizer can generate is determined by the range and step size of the divider numbers that can be selected.
Examples of prior art programmable frequency synthesizers are shown in FIGS. 1-3. In the programmable frequency synthesizer of FIG. 1, a voltage-controlled oscillator 10 generates the synthesizer output, F.sub.o, in the range between 1000 and 1400 MHz, in 2.0 MHz steps. A frequency divider 11 is provided by two fixed dividers 12 and 14 plus a programmable divider 16. The two fixed dividers 12 and 14 serve as a divide by twenty prescaler to reduce the frequency down to the 50 to 70 MHz range, to a point where the programmable divider 16 can be built using ECL circuitry. The programmable divider 16 divides its 50 to 70 MHz input signal by an integer between 500 and 700 to generate a feedback signal, F.sub.f, having a nominal frequency of 0.1 MHz. The feedback signal is compared to a reference signal, F.sub.r, by a phase detector 18, which generates an error signal in proportion to the phase or frequency difference between the feedback and reference signals. The error signal is amplified and fed back to the VCO 10, which adjusts the frequency of the synthesizer output signal up or down in order to reduce the error signal.
The overall divider number for the frequency divider 11 of FIG. 1 is between 10,000 and 14,000, with a step size of 20. The divider number is equal to the product of the divide numbers of the three dividers 12, 14, and 16, namely 4*5*A, where 4 and 5 are the divide numbers of the fixed dividers 12 and 14, respectively, and A is the divide number for the programmable divider 16. A has an integer value 500.ltoreq.A.ltoreq.700. The fixed portion of the frequency divider 11, dividers 12 and 14, divides by 20, while the programmable portion, divider 16, divides by a number between 500 and 700, for an overall divider number of between 10,000 and 14,000.
The phase noise performance of the programmable frequency synthesizer of FIG. 1 is limited by its high divider number and correspondingly low reference frequency. The noise floor, which is proportional to the divider number, is about 58 dBc. The programmable frequency synthesizer of FIG. 1 is limited in its phase noise performance by the large divider numbers necessary to achieve an acceptably small step size in the synthesizer output frequency. Also, switching speed is limited by the 0.1 MHz reference frequency.
The programmable frequency synthesizer illustrated in FIG. 2 improves upon the noise performance of the synthesizer of FIG. 1 by increasing the reference frequency by a factor of five without changing the effective step size. In the frequency divider 19 of FIG. 2, the fixed divider 14 and programmable divider 16 of the FIG. 1 synthesizer have been replaced by a dual modulus prescaler 20 and two programmable dividers 22 and 24. The dual modulus prescaler 20 divides the output signal from the fixed divider 12 by either of two consecutive integers, such as five or six, depending upon a control signal supplied by the programmable divider 24. The output signal from the dual modulus prescaler 20 clocks both programmable dividers 22 and 24. Programmable divider 22 divides the output signal from the dual modulus prescaler 20 by a value B, stored therein, and generates the feedback signal F.sub.f at a nominal frequency of 0.5 MHz. The value C, stored in programmable divider 24, determines how many times the dual modulus prescaler 20 will divide by six for each B number of cycles output from the dual modulus prescaler. For each B cycles, the dual modulus prescaler 20 will divide by six C times and will divide by five the remaining cycles, or B-C times. Both programmable dividers 22 and 24 include counters that are reset each B cycles by the feedback signal.
In frequency divider 19, the range of operation is determined by the values of B and C. As illustrated in FIG. 2, B is an integer 100.ltoreq.B.ltoreq.140, and C is an integer 0.ltoreq.C.ltoreq.4. The overall divider number, 2000 to 2800 in steps of 4, equals 4*(5*B+C) and includes a fixed divide by 4 component, provided by the fixed divider 12, and a programmable component of divide by 500 to 700 in steps of 1, provided by the dual modulus prescaler 20 and programmable dividers 22 and 24.
By way of examples, if a synthesizer output frequency of 1000 MHz is desired, then a value of B=100 is loaded into programmable divider 22 and a value of C=0 is loaded into programmable divider 24. These values yield an overall divider number of 2000 (=4*5*100), since the dual modulus prescaler 20 divides by five 100 times each 100 cycles. If the next higher synthesizer output frequency is desired, 1002 MHz, then a value of B=100 is loaded into programmable divider 22 and a value of C=1 is loaded into programmable divider 24, which causes the dual modulus prescaler 20 to divide by five 99 times out of 100 and divide by six 1 time out of 100, for an overall divider number of 2004 (=4*(5*100+1)). If the next higher synthesizer output frequency is desired, 1004 MHz, then a value of B=100 is loaded into programmable divider 22 and a value of C= 2 is loaded into programmable divider 24, which causes the dual modulus prescaler 20 to divide by five 98 times out of 100 and divide by six 2 times out of 100, for an overall divider number of 2008 (=4*(5*100+2)). To obtain a synthesizer output frequency of 1010 MHz, an overall divider number of 2020 (=4*(5*101+0)) is required, which is obtained by loading a B=101 into programmable divider 22 and a C=0 into programmable divider 24. The high end of the frequency range of the synthesizer output signal is reached by loading a value of B=140 into programmable divider 22.
In comparison with the previously described programmable frequency synthesizer, the synthesizer of FIG. 2 has its noise floor improved by a factor of 5, which increases the noise floor by 14 dBc to 72 dBc. This improvement in phase noise performance is achieved without adversely effecting the frequency range and step size of the synthesizer output signal. The loop bandwidth is also increased by a factor of five, which reduces the time needed to switch the loop.
Another prior art programmable frequency synthesizer, as illustrated in FIG. 3, provides a further reduction in divider number and a corresponding improvement in phase noise by using a technique known as fractional division, which allows non-integer division by the frequency divider 25. By using fractional division, the reference frequency used in the synthesizer of FIG. 3 has been increased by a factor of twenty, with a corresponding increase in phase noise performance.
In the synthesizer of FIG. 3, the frequency divider 25 consists of fixed divider 12, dual modulus prescaler 20, a programmable divider 26, a programmable fractional divider 28, a programmable counter 30, and an OR gate 32. The dual modulus prescaler 20 divides the frequency of the output signal from the fixed divider 12 by either of two successive integers, five or six, in response to control signals generated by the programmable counter 30 and the programmable fractional divider 28 and combined by the OR gate 32. The output signal from the dual modulus prescaler 20 clocks the programmable divider 26 and the programmable counter 30. Programmable divider 26 divides the output signal from the dual modulus prescaler 20 by a value D, stored therein, and generates the feedback signal F.sub.f at a nominal frequency of 10.0 MHz. The output signal of the programmable divider 26 also supplies a clocking signal to the programmable fractional divider 28 and a reset signal to the programmable counter 30.
The programmable counter 30 is clocked by the output signal of the dual modulus prescaler 20 and supplies to the dual modulus prescaler a divide-by-six control signal at a rate proportional to the value E stored therein. The rate at which the programmable counter 30 generates the divide-by-six control signal is equal to E/D, where D is the value stored in the programmable divider 26 and E is the value stored in the programmable counter 30. For each D pulses from the dual modulus prescaler, the programmable counter 30 causes the dual modulus prescaler 20 to divide by six E times, where D is equal to either 5 or 6, and E is an integer and 0.ltoreq.E.ltoreq.4. In other words, the programmable counter 30 causes the dual modulus prescaler 20 to divide by six either 0/D, 1/D, 2/D, 3/D, or 4/D of the time, depending on the value of E. The programmable counter 30 is reset each D clock pulses by the output signal from the programmable divider 26.
The programmable fractional divider 28 is clocked by the output signal of the programmable divider 26 and supplies to the dual modulus prescaler a divide-by-six control signal at a rate proportional to the value F stored therein. For each twenty pulses from the programmable divider 26, the programmable fractional divider 28 causes the dual modulus prescaler to divide by six F times, where F is an integer and 0.ltoreq.F.ltoreq.20. Since the programmable fractional divider 28 is clocked at a rate equal to 1/D of the programmable counter 30, the programmable fractional divider causes the dual modulus prescaler to divide by six by a factor equal to F/20*D.
The OR gate 32 combines the two divide-by-six control signals generated by the programmable fractional divider 28 and programmable counter 30 and supplies to the dual modulus prescaler 20 a signal that determines which divisor (five or six) is used. The operation of the programmable fractional divider 28 and the programmable counter 30 are coordinated so that their control signals do not overlap.
The range in synthesizer output frequency provided by the divide by 5/6 dual modulus prescaler 20 is 20% of the lowest frequency, so to get a frequency adjustment range comparable to that of synthesizers of FIGS. 1 and 2, about 40%, the programmable divider 26 is used. The frequency divider 25 operates within two regions: (1) a lower frequency region where D=5 and the overall divider number is 100.00 to 120.00 in steps of 0.20, which results in a range of synthesizer output frequencies between 1000 and 1200 MHz in steps of 2.0 MHz; and (2) a higher frequency region where D=6 and the overall divider number is 120.00 to 140.00 in steps of 0.20, which results in a range of synthesizer output frequencies between 1200 and 1400 MHz in steps of 2.0 MHz.
The range of operation of frequency divider 25 is determined by the values of D, E, and F. As illustrated in FIG. 3, D is either 5 or 6, E is an integer 0.ltoreq.E.ltoreq.4, and F is an integer 0.ltoreq.F.ltoreq.20. The overall divider number equals 4*(5*D+E+F/20), or 20*D+4*E+F/5, and includes a fixed divide by 4 component, provided by the fixed divider 12, and a programmable component of divide by 25.00 to 35.00 in steps of 0.05, provided by the rest of the frequency divider circuitry. The frequency divider 25 has a divider number of 4*D*5 when the dual modulus prescaler 20 is dividing by five and 4*D*6 when the dual modulus prescaler is dividing by six. The effective, or overall, divider number is the weighted average of those two divider numbers.
By way of example, if a synthesizer output frequency of 1000 MHz is desired, then a value of D=5 is loaded into programmable divider 26, a value of F=0 is loaded into programmable fractional divider 28, and a value of E=0 is loaded in programmable counter 30. These values yield an overall divider number of 100.0, since the fixed divider 20 divides by four, the programmable divider 26 divides by five, and the dual modulus prescaler 20 divides by five all the time.
If the next higher synthesizer output frequency is desired, 1002 MHz, then a value of F=1 is loaded into programmable fractional divider 28, with D=5 and E=0, which causes the dual modulus prescaler 20 to divide by five (divider number=100) 99 times out of 100 and divide by six (divider number=120) 1 time out of 100, which works out to be an average divide number of 100.2. To obtain a synthesizer output frequency of 1040 MHz, for example, an overall divider number of 104.0 is required, which is obtained by loading F=0 into programmable fractional divider 28 and E=1 into programmable counter 30.
The upper half of the frequency range of the synthesizer output signal is reached by loading a value of D=6 into programmable divider 26. To obtain a synthesizer output frequency of 1200 MHz, an overall divider number of 120.0 is required, which is obtained by loading F=0 into programmable fractional divider 28 and E=0 into programmable counter 30. If the next higher synthesizer output frequency is desired, 1202 MHz, then a value of F=1 is loaded into programmable fractional divider 28, with D=6 and E=0, which causes the dual modulus prescaler 20 to divide by five (divider number=120) 119 times out of 120 and divide by six (divider number=144) 1 time out of 120, which works out to be an average divide number of 120.2. The maximum synthesizer output frequency of 1400 MHz is achieved by loading values of D=6, E=4, and F=20 into the corresponding dividers and counters.
In comparison to the programmable frequency synthesizer of FIG. 2, the synthesizer of FIG. 3 has its phase noise performance improved by a factor of 20, which increases the noise floor to about 98 dBc. This improvement in phase noise performance is achieved by the use of a fractional divider, with the effect of slightly changing the frequency range and step size of the synthesizer output signal, due to the operation of the programmable divider 26.
These prior art synthesizer designs show an evolution to higher reference frequencies in order to improve phase noise performance. What is needed, however, is another means for further increasing the reference frequency in order to further improve phase noise performance.